A SIMDizing C Compiler for the Mitsubishi Electric Neuro4 Processor Array

Mitsubishi Electric Neuro4 is a high performance parallel processing engine for neural network, image processing and signal processing applications. The Neuro4 chip employs a distributed memory SIMD architecture with twelve 24-bit floating-point processing units (PUs), a nonlinear function unit (NFU), and a control unit (CU). A Neuro4 board consists of four Neuro4 chips. In this paper, we present work in progress on a SIMDizing compiler based on the SUIF Compiler System, for the Neuro4 processor array. We present the organization of the SIMDizer for the Neuro4 system. We discuss the issues of data distribution, array data coherency between the host workstation and Neuro4 board, and Neuro4 code generation, in detail. We also describe the new compiler issues a SIMDizer has to tackle specific to this type of system. The high performance Neuro4 system and its SIMDizer facilitates, at a much lower cost, computationally intensive applications which are difficult to perform on conventional workstations or on low end supercomputers.